Jlink | V9 Schematic ((new))

The standard V9 schematic includes a 20-pin IDC connector with the following primary connections: Description VTref Target Reference Voltage (1.2V–5V) 2 NC / 5V-Supply Often not connected; can be used for 5V target power 3 nTRST JTAG Reset (Active low) 7 TMS / SWDIO JTAG Mode Select / SWD Data 9 TCK / SWCLK JTAG Clock / SWD Clock 13 TDO / SWO JTAG Data Out / SWD Trace Output 15 nRESET Target CPU Reset 4-20 (even) GND Common ground pins Original vs. Clone Schematics

| Pin | Signal | Connection in V9 | | :--- | :--- | :--- | | 1 | VTref | Goes to Level Shifter VCC_B and ADC of STM32 (to measure voltage) | | 2 | SWDIO (TMS) | Level Shifter Channel 1 -> MCU PA13 | | 4 | SWCLK (TCK) | Level Shifter Channel 2 -> MCU PA14 | | 6 | SWO (TDO) | Level Shifter Channel 3 -> MCU PB3 | | 8 | nTRST | Level Shifter -> MCU (if available) | | 10 | nRESET | Gate of 2N7002 -> MCU (Open drain) | | 15 | nSRST | Same as nRESET usually | | 3,5,7,9 | GND | Ground plane | jlink v9 schematic

Why is the schematic so popular?

The J-Link V9 uses a .

The J-Link V9 schematic is a masterclass in robust debug tool design. It separates power domains, uses a high-performance MCU with hardware USB, and implements intelligent voltage detection. The standard V9 schematic includes a 20-pin IDC