| Week | Topic | Lab Component | |------|-------|----------------| | 1 | Review of classic 5-stage pipeline hazards | Toolchain setup (Gem5, Simics, or Sniper simulator) | | 2 | Dynamic scheduling with Tomasulo’s algorithm | Simulating scoreboarding vs. register renaming | | 3 | Branch prediction (tournament predictors, TAGE) | Implementing a custom predictor in C++ | | 4 | Out-of-order execution (ROB, issue queues) | Modifying a simple OoO simulator | | 5 | Memory disambiguation and store-to-load forwarding | Cache coherence simulation (MSI/MESI) | | 6 | VLIW and EPIC architectures | Analyzing Itanium code traces | | 7 | Midterm exam | No lab; exam review session | | 8 | Vector processors (Cray-1 to modern SIMD) | Writing AVX-2/AVX-512 intrinsics | | 9 | GPU architecture (NVIDIA Volta/Ampere/Hopper) | CUDA kernel optimization for matrix multiply | | 10 | Multi-core cache coherence (MESI, MOESI) | Running a directory-based coherence protocol | | 11 | Memory consistency models (TSO, RC, ARMv8) | Detecting data races in concurrent C++ | | 12 | Hardware transactional memory (HTM) | Testing HTM on Intel TSX (or gem5) | | 13 | Prefetching and speculation | Evaluating stride vs. Markov prefetchers | | 14 | Domain-specific accelerators (DSA) | Designing a simple tensor accelerator in Verilog/C | | 15 | Research paper presentations | Group project finalization | | 16 | Final exam + project demos | Submission of final report and code |
While specific syllabi for this exact alphanumeric code can vary by university (such as those found in catalogs like West Chester University or Sacramento State ), a "useful guide" for a level-5000 CSC course typically centers on mastering technical efficiency and professional-grade implementation. csc5113c
FSMs are the brains of digital control logic. Students learn to design Moore and Mealy machines to control data paths. This is crucial for implementing protocols, bus controllers, and the fetch-decode-execute cycles of a CPU. | Week | Topic | Lab Component |
Detects rapid spikes in current (during both charging and discharging) and immediately disconnects the circuit to prevent fire or damage to the device. FSMs are the brains of digital control logic
Cuts off power when the battery voltage drops too low, preserving the chemical health and lifespan of the 18650 or similar cells.
Teams implement a simplified in a distributed simulation environment. They must handle transient states, race conditions, and invalidation traffic. The final step is to compare directory-based vs. snooping approaches in terms of bandwidth consumption.